/*
 * Copyright (C) 2018 Unigroup Spreadtrum & RDA Technologies Co., Ltd.
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 * updated at 2018-12-18 10:53:49
 *
 */


#ifndef ANLG_PHY_G13_H
#define ANLG_PHY_G13_H

#define CTL_BASE_ANLG_PHY_G13 0x32404000


#define REG_ANLG_PHY_G13_ANALOG_PCIEPLL_H_PCIEPLL_H_CTRL0      ( CTL_BASE_ANLG_PHY_G13 + 0x0000 )
#define REG_ANLG_PHY_G13_ANALOG_PCIEPLL_H_PCIEPLL_H_CTRL1      ( CTL_BASE_ANLG_PHY_G13 + 0x0004 )
#define REG_ANLG_PHY_G13_ANALOG_PCIEPLL_H_PCIEPLL_H_CTRL2      ( CTL_BASE_ANLG_PHY_G13 + 0x0008 )
#define REG_ANLG_PHY_G13_ANALOG_PCIEPLL_H_PCIEPLL_H_CTRL3      ( CTL_BASE_ANLG_PHY_G13 + 0x000C )
#define REG_ANLG_PHY_G13_ANALOG_PCIEPLL_H_PCIEPLL_H_CTRL6      ( CTL_BASE_ANLG_PHY_G13 + 0x0010 )
#define REG_ANLG_PHY_G13_ANALOG_PCIEPLL_H_PCIEPLL_H_CTRL7      ( CTL_BASE_ANLG_PHY_G13 + 0x0014 )
#define REG_ANLG_PHY_G13_ANALOG_PCIEPLL_H_PCIEPLL_H_CTRL8      ( CTL_BASE_ANLG_PHY_G13 + 0x0018 )
#define REG_ANLG_PHY_G13_ANALOG_PCIEPLL_H_PCIEPLL_H_CTRL4      ( CTL_BASE_ANLG_PHY_G13 + 0x001C )
#define REG_ANLG_PHY_G13_ANALOG_PCIEPLL_H_PCIEPLL_H_CTRL5      ( CTL_BASE_ANLG_PHY_G13 + 0x0020 )
#define REG_ANLG_PHY_G13_ANALOG_PCIEPLL_H_REG_SEL_CFG_0        ( CTL_BASE_ANLG_PHY_G13 + 0x0024 )

/* REG_ANLG_PHY_G13_ANALOG_PCIEPLL_H_PCIEPLL_H_CTRL0 */

#define BIT_ANLG_PHY_G13_ANALOG_PCIEPLL_H_RG_PCIEPLLH_REFCK_SEL(x)        (((x) & 0x7) << 29)
#define BIT_ANLG_PHY_G13_ANALOG_PCIEPLL_H_RG_PCIEPLLH_CLKOUTEXT_EN        BIT(28)
#define BIT_ANLG_PHY_G13_ANALOG_PCIEPLL_H_RG_PCIEPLLH_PD                  BIT(27)
#define BIT_ANLG_PHY_G13_ANALOG_PCIEPLL_H_RG_PCIEPLLH_RST                 BIT(26)
#define BIT_ANLG_PHY_G13_ANALOG_PCIEPLL_H_RG_PCIEPLLH_N(x)                (((x) & 0x7FF) << 15)
#define BIT_ANLG_PHY_G13_ANALOG_PCIEPLL_H_RG_PCIEPLLH_CLKOUTEN            BIT(14)
#define BIT_ANLG_PHY_G13_ANALOG_PCIEPLL_H_RG_PCIEPLLH_DIVN(x)             (((x) & 0x1F) << 9)
#define BIT_ANLG_PHY_G13_ANALOG_PCIEPLL_H_RG_PCIEPLLH_BIST_CTRL(x)        (((x) & 0xFF) << 1)
#define BIT_ANLG_PHY_G13_ANALOG_PCIEPLL_H_DIFF_OR_SING_SEL                BIT(0)

/* REG_ANLG_PHY_G13_ANALOG_PCIEPLL_H_PCIEPLL_H_CTRL1 */

#define BIT_ANLG_PHY_G13_ANALOG_PCIEPLL_H_RG_PCIEPLLH_NINT(x)             (((x) & 0xFF) << 20)
#define BIT_ANLG_PHY_G13_ANALOG_PCIEPLL_H_RG_PCIEPLLH_KINT(x)             (((x) & 0xFFFFF))

/* REG_ANLG_PHY_G13_ANALOG_PCIEPLL_H_PCIEPLL_H_CTRL2 */

#define BIT_ANLG_PHY_G13_ANALOG_PCIEPLL_H_RG_PCIEPLLH_SSC_DIV(x)          (((x) & 0x7) << 16)
#define BIT_ANLG_PHY_G13_ANALOG_PCIEPLL_H_RG_PCIEPLLH_KDELTA(x)           (((x) & 0xFFFF))

/* REG_ANLG_PHY_G13_ANALOG_PCIEPLL_H_PCIEPLL_H_CTRL3 */

#define BIT_ANLG_PHY_G13_ANALOG_PCIEPLL_H_RG_PCIEPLLH_KSTEP(x)            (((x) & 0x7FFFF) << 6)
#define BIT_ANLG_PHY_G13_ANALOG_PCIEPLL_H_RG_PCIEPLLH_SDM_EN              BIT(5)
#define BIT_ANLG_PHY_G13_ANALOG_PCIEPLL_H_RG_PCIEPLLH_MOD_EN              BIT(4)
#define BIT_ANLG_PHY_G13_ANALOG_PCIEPLL_H_RG_PCIEPLLH_DIV_S               BIT(3)
#define BIT_ANLG_PHY_G13_ANALOG_PCIEPLL_H_BG_RBIAS_MODE                   BIT(2)
#define BIT_ANLG_PHY_G13_ANALOG_PCIEPLL_H_RG_PCIEPLLH_PREDIV              BIT(1)
#define BIT_ANLG_PHY_G13_ANALOG_PCIEPLL_H_RG_PCIEPLLH_POSTDIV             BIT(0)

/* REG_ANLG_PHY_G13_ANALOG_PCIEPLL_H_PCIEPLL_H_CTRL6 */

#define BIT_ANLG_PHY_G13_ANALOG_PCIEPLL_H_RG_PCIEPLLH_RESERVED(x)         (((x) & 0x1FFFFF))

/* REG_ANLG_PHY_G13_ANALOG_PCIEPLL_H_PCIEPLL_H_CTRL7 */

#define BIT_ANLG_PHY_G13_ANALOG_PCIEPLL_H_RG_PCIEPLLH_BIST_EN             BIT(20)
#define BIT_ANLG_PHY_G13_ANALOG_PCIEPLL_H_RG_PCIEPLLH_BIST_CNT(x)         (((x) & 0xFFFF) << 4)
#define BIT_ANLG_PHY_G13_ANALOG_PCIEPLL_H_RG_PCIEPLLH_LOCKDONE            BIT(3)
#define BIT_ANLG_PHY_G13_ANALOG_PCIEPLL_H_PCIEPLLH_DUTY_FIT_EN            BIT(2)
#define BIT_ANLG_PHY_G13_ANALOG_PCIEPLL_H_PCIEPLLH_26MBUFFER_BIASSEL(x)   (((x) & 0x3))

/* REG_ANLG_PHY_G13_ANALOG_PCIEPLL_H_PCIEPLL_H_CTRL8 */

#define BIT_ANLG_PHY_G13_ANALOG_PCIEPLL_H_PCIEPLLH_26MBUFFER_PD           BIT(11)
#define BIT_ANLG_PHY_G13_ANALOG_PCIEPLL_H_PCIEPLLH_26MBUFFER_TEST_EN      BIT(10)
#define BIT_ANLG_PHY_G13_ANALOG_PCIEPLL_H_PCIEPLLH_LDOOUT_SEL(x)          (((x) & 0x3) << 8)
#define BIT_ANLG_PHY_G13_ANALOG_PCIEPLL_H_RG_PCIEPLLH_ICP(x)              (((x) & 0x7) << 5)
#define BIT_ANLG_PHY_G13_ANALOG_PCIEPLL_H_RG_PCIEPLLH_CP_EN               BIT(4)
#define BIT_ANLG_PHY_G13_ANALOG_PCIEPLL_H_RG_PCIEPLLH_LDO_TRIM(x)         (((x) & 0xF))

/* REG_ANLG_PHY_G13_ANALOG_PCIEPLL_H_PCIEPLL_H_CTRL4 */

#define BIT_ANLG_PHY_G13_ANALOG_PCIEPLL_H_RG_PCIEPLLH_R2_SEL(x)           (((x) & 0x7) << 23)
#define BIT_ANLG_PHY_G13_ANALOG_PCIEPLL_H_RG_PCIEPLLH_R3_SEL(x)           (((x) & 0x3) << 21)
#define BIT_ANLG_PHY_G13_ANALOG_PCIEPLL_H_RG_PCIEPLLH_C2_SEL(x)           (((x) & 0x7) << 18)
#define BIT_ANLG_PHY_G13_ANALOG_PCIEPLL_H_RG_PCIEPLLH_KVCO_SEL(x)         (((x) & 0x7) << 15)
#define BIT_ANLG_PHY_G13_ANALOG_PCIEPLL_H_RG_PCIEPLLH_VCO_TEST_EN         BIT(14)
#define BIT_ANLG_PHY_G13_ANALOG_PCIEPLL_H_RG_PCIEPLLH_VCO_TEST_INT        BIT(13)
#define BIT_ANLG_PHY_G13_ANALOG_PCIEPLL_H_RG_PCIEPLLH_VCO_TEST_INTSEL(x)  (((x) & 0x7) << 10)
#define BIT_ANLG_PHY_G13_ANALOG_PCIEPLL_H_RG_PCIEPLLH_SHORT_CSR_EN        BIT(9)
#define BIT_ANLG_PHY_G13_ANALOG_PCIEPLL_H_RG_PCIEPLLH_ALLOP_PD            BIT(8)
#define BIT_ANLG_PHY_G13_ANALOG_PCIEPLL_H_RG_PCIEPLLH_TEST_VCO_PN         BIT(7)
#define BIT_ANLG_PHY_G13_ANALOG_PCIEPLL_H_RG_PCIEPLLH_MANUAL_ADJ_PD       BIT(6)
#define BIT_ANLG_PHY_G13_ANALOG_PCIEPLL_H_RG_PCIEPLLH_FBDIV_EN            BIT(5)
#define BIT_ANLG_PHY_G13_ANALOG_PCIEPLL_H_RG_PCIEPLLH_VCOBUF_EN           BIT(4)
#define BIT_ANLG_PHY_G13_ANALOG_PCIEPLL_H_RG_PCIEPLLH_CP_OFFSET(x)        (((x) & 0x7) << 1)
#define BIT_ANLG_PHY_G13_ANALOG_PCIEPLL_H_RG_PCIEPLLH_DOUBLER_EN          BIT(0)

/* REG_ANLG_PHY_G13_ANALOG_PCIEPLL_H_PCIEPLL_H_CTRL5 */

#define BIT_ANLG_PHY_G13_ANALOG_PCIEPLL_H_RG_PCIEPLLH_CALI_MODE(x)        (((x) & 0x3) << 25)
#define BIT_ANLG_PHY_G13_ANALOG_PCIEPLL_H_RG_PCIEPLLH_CALI_INI(x)         (((x) & 0x1F) << 20)
#define BIT_ANLG_PHY_G13_ANALOG_PCIEPLL_H_RG_PCIEPLLH_CALI_TRIG           BIT(19)
#define BIT_ANLG_PHY_G13_ANALOG_PCIEPLL_H_RG_PCIEPLLH_CALI_WAITCNT(x)     (((x) & 0x3) << 17)
#define BIT_ANLG_PHY_G13_ANALOG_PCIEPLL_H_RG_PCIEPLLH_CALI_POLARITY       BIT(16)
#define BIT_ANLG_PHY_G13_ANALOG_PCIEPLL_H_RG_PCIEPLLH_VCTRLH_SEL(x)       (((x) & 0x7) << 13)
#define BIT_ANLG_PHY_G13_ANALOG_PCIEPLL_H_RG_PCIEPLLH_VCTRLL_SEL(x)       (((x) & 0x7) << 10)
#define BIT_ANLG_PHY_G13_ANALOG_PCIEPLL_H_RG_PCIEPLLH_CALI_DONE           BIT(9)
#define BIT_ANLG_PHY_G13_ANALOG_PCIEPLL_H_RG_PCIEPLLH_CALI_OUT(x)         (((x) & 0x1F) << 4)
#define BIT_ANLG_PHY_G13_ANALOG_PCIEPLL_H_RG_PCIEPLLH_CALI_CPPD           BIT(3)
#define BIT_ANLG_PHY_G13_ANALOG_PCIEPLL_H_RG_PCIEPLLH_FREQ_DIFF_EN        BIT(2)
#define BIT_ANLG_PHY_G13_ANALOG_PCIEPLL_H_RG_PCIEPLLH_CALI_VCTRL_HIGH     BIT(1)
#define BIT_ANLG_PHY_G13_ANALOG_PCIEPLL_H_RG_PCIEPLLH_CALI_VCTRL_LOW      BIT(0)

/* REG_ANLG_PHY_G13_ANALOG_PCIEPLL_H_REG_SEL_CFG_0 */

#define BIT_ANLG_PHY_G13_DBG_SEL_ANALOG_PCIEPLL_H_RG_PCIEPLLH_REFCK_SEL   BIT(4)
#define BIT_ANLG_PHY_G13_DBG_SEL_ANALOG_PCIEPLL_H_RG_PCIEPLLH_PD          BIT(3)
#define BIT_ANLG_PHY_G13_DBG_SEL_ANALOG_PCIEPLL_H_RG_PCIEPLLH_RST         BIT(2)
#define BIT_ANLG_PHY_G13_DBG_SEL_ANALOG_PCIEPLL_H_RG_PCIEPLLH_CLKOUTEN    BIT(1)
#define BIT_ANLG_PHY_G13_DBG_SEL_ANALOG_PCIEPLL_H_PCIEPLLH_26MBUFFER_PD   BIT(0)


#endif /* ANLG_PHY_G13_H */


